Semiconductor devices typically have large numbers of conductive structures which need to be interconnected. Such conductive structures include, for example, silicon regions separated by a dielectric region. The conductive structures are interconnected by forming a "bridge contact" or "strap" between the structures.
Refractory metals and refractory metal silicides have often been used for interconnecting conductive structures. These materials possess low resistivity characteristics normally associated with metals such as aluminum and copper, without providing the manufacturing challenges inherent in these materials (heat sensitivity in the case of aluminum, patterning difficulties in the case of copper). Typically, silicide electrodes are formed on silicon diffusion regions by depositing the refractory metal layer on the substrate, heating the metal to form silicide regions over the exposed silicon regions, and treating the substrate in a wet etchant to remove the unreacted refractory metal.
This silicide forming method poses problems in that the method may consume up to several microns of the underlaying silicon in forming the silicide. This consumption has the effect of greatly reducing the effective dopant concentrations at the silicide/diffusion interface, which can have negative effects on the characteristics of the semiconductor device.
Several solutions have been suggested to remedy this problem. One method is to co-deposit the refractory metal with silicon, such that upon annealing a lesser amount of the junction silicon will be consumed. See U.S. Pat. No. 4,663,191, issued May 5, 1987 to Choi et al. Another technique is to provide additional silicon on top of the junction regions, which will be consumed instead of the underlying silicon. See IBM Technical Disclosure Bulletin, Vol. 20, No. 9, pages 3480-3483 (February 1978).
Others have approached the need for interconnecting conductive structures by utilizing other types of materials, as opposed to refractory metals and refractory metal silicides. For example, the article entitled "Diffusion Defined Bridge Contact" (IBM Technical Disclosure Bulletin, Vol. 29, No. 8, page 3423 [January 1987]) discloses the general concept of employing dopant out-diffusion to define a surface contact between a polysilicon region and a silicon region over a dielectric.
The following references disclose the formation of silicide bridge contacts for connecting a polysilicon-filled trench to a source/drain region over a dielectric: U.S. Pat. No. 4,873,205 (issued Oct. 10, 1989); U.S. Pat. No. 4,983,544 (issued Jan. 8, 1991); "CMOS Process For Titanium Salicide Bridging Of A Trench and Simultaneously Allowing For True Gate Isolation", IBM Technical Disclosure Bulletin, Vol. 29, No. 3 (Aug. 1986), pp. 1037-1038; "Self-Aligned Electrical Connection To Trench", IBM Technical Disclosure Bulletin, Vol. 29, No. 3 (August 1986), pp. 1421-1422; "Multi-Purpose Trench for Complementary Metal Oxide Silicon, Six-Device Static Random-Access Memory Cell", IBM Technical Disclosure Bulletin, Vol. 32, No. 9A (February 1990), p. 433; and U.S. Pat. No. 4,745,081 (issued May 17, 1988). None of the references in this group, however, employs a dopant out-diffusion technique.
In the following group of references, a dopant out-diffusion process was used in the formation of structures other than straps or bridge contacts:
U.S. Pat. No. 4,502,894 (issued Mar, 5, 1985) discloses a process for producing polysilicon resistors, by employing boron out-diffusion. After forming oxide regions, boron or other dopant is implanted into the oxide. A layer of polysilicon is then deposited and patterned, and the structure is treated to cause boron to out-diffuse into the polysilicon. PA1 Japanese Pat. No. 62-122124 (issued Jun. 3, 1987) discloses a process for out-diffusion of boron into an overlying polysilicon layer. After a silicon dioxide film is grown onto a silicon substrate a boron phosphorus silicate glass (BPSG) film is deposited. A contact hole is then formed in the BPSG and the oxide layers, followed by deposition of a polysilicon layer. The structure is then heated to effect boron out-diffusion from the BPSG layer into the polysilicon layer. PA1 U.S. Pat. No. 4,654,121 (issued Mar. 31, 1987) discloses a process for forming stacked CMOS devices. After forming the lower device, an undoped oxide layer and then a doped oxide layer are formed. A planarizing step is then carried out to expose the gate electrode and to form doped oxide regions to the sides of the gate. An upper gate oxide is grown and a polysilicon layer defined over the oxide. The source and drain regions for the upper device are then formed by boron out-diffusion from the lower doped oxide regions.
U.S. Pat. No. 4,782,036 (issued Nov. 1, 1988) discloses a process for doping the sidewalls and base of a trench. After the trench formation in a silicon substrate, a borosilicate glass layer is deposited by decomposition of TEOS and trimethylborate. Then, the structure is treated to cause boron to diffuse into the sidewalls and base, followed by removal of the glass layer.
Despite these approaches to strap formation, a need continues to exist for methods for forming a low resistance connection between conductive structures which can readily be utilized in the fabrication of semiconductor devices at minimal manufacturing expense.